甘肃甘南Speedgoat系统
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西南交通大学-竞价公告 (CB***************)发布时间：****-**-** **:**基本信息：申购单主题：Speedgoat系统申购单类型：竞价类设备类别：**.仪器仪表使用币种：人民币竞价开始时间：****-**-** **:** 竞价结束时间：****-**-** **:** 申购备注：经费人：高仕斌 申购设备详情：设备名称数量单位品牌型号是否标配售后服务规格配置附件Speedgoat系统*套Speedgoat见附件是*、按行业标准提供服务； *、是否要求本地有售后服务网点：（B） A.是 B.否 “本地”指采购单位所在省级行政区域；有售后服务网点的证明材料包括：******营业执照，当地某公************之间签订的有效合作协议。本地供应商无需上传证明文件；外地供应商需上传当地服务网点证明文件压缩包。*.Performance real-time target machine：Complete, fully assembled, and tested Performance real-time target machine. sixth (latest) generation Intel Core i* dual core *.* GHz CPU, ****MB RAM, ***GB flash device, * x PCIe and * x PCI I/O slots, *x Gigabit Ethernet ports ， *x COM port (RS***) supporting baud rates up to ***kbs, USB port for kernel transfer, * x PS/* keyboard port, and * xVGA, * x DisplayPort and * x HDMI for target screen.
*. Performance-CPUCorei*****：*th generation Intel Core i* *.*GHz CPU with four cores instead of Intel Core i* dual core *.* GHz CPU.
*. IO***：Low latency **-bit analog I/O module with ** x differential simultaneous analog input channels supporting voltage ranges of +/- **V and +/- *V, and * x *.*/*V digital TTL I/O lines individually configurable as input or output.
*. IO***:：Versatile and configurable Spartan * FPGA-based I/O module with ***k of logic
cells and fast speedgrade *, with ** single-ended or ** differential **-bit analog inputs with a total of * AD converters supporting simultaneous acquisition for up to * AD channels, * x **-bit analog outputs
*. IO*** HDL Coder Integration Package：Reference design for the selected IO**x/IO**x FPGA I/O module, to run Simulink designs on the FPGA leveraging automatic VHDL Code generation with HDL Coder from MathWorks.登陆后可下载附件竞价报名网址:http://***.******.***/biddingShow/*******A-BD*C-*DB*-*BED-**A*A*******
